Jens Spinner

Institute of System Dynamics

Contact

Hochschule Konstanz für Technik, Wirtschaft und Gestaltung
Alfred-Wachtel-Str. 8
78462 Konstanz

Room E 202
+49 7531 206-461
jens.spinner@htwg-konstanz.de

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Publications

  • 2016
    • Jens Spinner, Mohammed Rajab, and Jürgen Freudenberger. Construction of high-rate generalized concatenated codes for applications in non-volatile flash memories. In IEEE 8th Int. Memory Workshop (IMW), pages 1–4, May 2016.[ DOI ]
    • Jens Spinner, Jürgen Freudenberger, and Sergo Shavgulidze. A soft input decoding algorithm for generalized concatenated codes. IEEE Transactions on Communications, 64(9):3585–3595, Sept 2016.[ DOI ]
  • 2015
    • Jens Spinner and Jürgen Freudenberger. Soft input decoding of generalized concatenated codes using a stack decoding algorithm. In 2nd BW-CAR Symp. on Information and Communication Systems (SInCom), November 2015.
    • Jürgen Freudenberger and Sergo Shavgulidze. New four-dimensional signal constellations from Lipschitz integers for transmission over the Gaussian channel. IEEE Transactions on Communications, 2015.[ DOI | http ]
    • Jürgen Freudenberger, Thomas Wegmann, and Jens Spinner. An efficient hardware implementation of sequential stack decoding of binary block codes. 5th IEEE Int. Conf. on Consumer Electronics, 2015.
    • Jens Spinner and Jürgen Freudenberger. Datenrettung für die Speicherkarte – Fehlerkorrekturverfahren für Flash-Speicher. horizonte, 45:18–20, 2015.[ .pdf  ]
    • Jens Spinner and Jürgen Freudenberger. Decoder architecture for generalized concatenated codes. IET Circuits, Devices & Systems, 9(5):328–335, 2015.[ DOI ]
  • 2014
    • Jens Spinner and Jürgen Freudenberger. Eine effiziente Dekoderarchitektur für verallgemeinert verkettete Codes. MPC-Workshop Künzelsau, 52:27–31, June 2014.[ .pdf ]
    • Jürgen Freudenberger, Jens Spinner, and Sergo Shavgulidze. Set partitioning of Gaussian integer constellations and its application to two-dimensional interleaving. IET Communications, 8(8):1336–1346, May 2014.
    • Jürgen Freudenberger, Jens Spinner, and Sergo Shavgulidze. Set partitioning of Gaussian integer constellations and its application to two-dimensional interleaver design. In Int. Conf. on Communication and Signal Processing (CSP), 2014.
    • Jürgen Freudenberger, Jens Spinner, and Sergo Shavgulidze. Generalized concatenated codes for correcting two-dimensional clusters of errors and independent errors. In Int. Conf. on Communication and Signal Processing (CSP), 2014.
    • Jens Spinner and Jürgen Freudenberger. Design and implementation of a pipelined decoder for generalized concatenated codes. In 27th Symp. on Integrated Circuits and Systems Design (SBCCI), Aracaju, Brazil, pages 1–6, 2014.[ DOI | http ]
    • Jens Spinner, Jürgen Freudenberger, and Sergo Shavgulidze. Sequential decoding of binary block codes based on supercode trellises. In 1. Baden-Württemberg Center of Applied Research Symp. on Information and Communication Systems, 2014.[ http ]
  • 2013
    • Jürgen Freudenbergerand Jens Spinner. A configurable Bose-Chaudhuri-Hocquenghem codec architecture for flash controller applications. Journal of Circuits, Systems, and Computers, 2013.[ DOI | http  ]
    • Jens Spinner, Jürgen Freudenberger, Christoph Baumhof, and Axel Mehnert. A BCH decoding architecture with mixed parallelization degrees for flash controller applications. In 26 th IEEE Int. SoC Conf. (SOCC), 2013.
  • 2012
    • Jürgen Freudenberger and Jens Spinner. Mixed serial/parallel hardware implementation of the Berlekamp-Massey algorithm for BCH decoding in flash controller applications. 2012.[ http ]
    • Jürgen Freudenberger, Uwe Kaiser, and Jens Spinner. Concatenated code constructions for error correction in non-volatile memories. Int. Symp. on Signals, Systems and Electronics, 2012.[ http ]
    • Jens Spinner and Jürgen Freudenberger. Hardware-entwurf einer flexiblen fehlerkorrektureinheit für flashspeicher. 48. MPC-Workshop, Aalen, 2012.[ http ]
    • Jens Spinner and Jürgen Freudenberger. Semi-automatic source code generation for the hardware- implementation of a parallelizable and configurable error correction unit. In 8th Conf. on Ph.D. Research in Microelectronics & Electronics, Aachen, 2012.[ http  ]
    • Jens Spinner and Jürgen Freudenberger. Generierung von codecomponenten für BCH encodierer. In 47. MPC-Workshop, Offenburg,, 2012.[ http ]